The present invention relates to a semiconductor device and a method for manufacturing the same. More particularly, the present invention relates to a semiconductor device which enables increased integration, and a method for manufacturing the same.
Integrating the maximum number of devices in the minimum cell area is important for increasing the integration of a semiconductor memory cell, and particularly, of a dynamic random access memory (DRAM) cell.
In a next-generation 1 Gb DRAM, the memory cell composed of one transistor and one capacitor occupies an area of 0.3 .mu.m.sup.2 or less. This is the same area as previously needed for just the contact hole for interconnection in a one mega-bit DRAM cell. Forming one transistor; one capacitor, and one contact hole for interconnection all together in such a small area to form a unit cell, is practically impossible with current technology. Particularly, current layout methods have reached a bottleneck in terms of area limitation, so that a novel scheme for achieving the above has become necessary.
In most memory cells now incorporated in chips, a transistor, a capacitor and a contact hole are formed laterally on a planar layout, and the total area thereof acts as a factor in determining the area of the memory cell. Accordingly, since a transistor, a capacitor, and a contact hole for connection of the source and drain regions are formed in an area of 0.3 .mu.m.sup.2 or less for constituting a giga-bit memory cell, a three-dimensional cell structure is needed to overcome area limitations, and the cell structure must be altered from a lateral layout structure into a vertical layout structure.
While there exists a trench structure or a stacked structure as a typical example of such a three-dimensional cell structure, these structures cannot satisfy a capacitance requirement for next-generation devices.
T. Ozaki el al. suggest a SIMPLE cell wherein the capacitor area can be increased while an isolation region area is minimized (see IEDM '91, "A Surrounding Isolation-merged Plate Electrode (SIMPLE) Cell with Checkered Layout for 256 Mbit DRAMs and Beyond"). However, since the process for connecting the source region of a transistor with a capacitor's storage-node in the SIMPLE cell is a lateral scheme, a contact hole area for connection is needed. Also, a contact hole area for connecting a drain region with a bit-line is needed. Therefore, according to the SIMPLE cell structure, though a design rule of 0.1 .mu.m is used, unit DRAM elements cannot be formed within an area of 0.3 .mu.m.sup.2, and thus, forming the memory cell for giga bit DRAMs and beyond is impossible.
K. Sunouchi et al. suggest a SGT cell wherein all the devices for the unit memory cell are formed in one silicon pillar isolated by a matrix-like trench (see IEDM '89, "A Surrounding Gate Transistor (SGT) cell for 64 and 256 Mbit DRAMs"). However, in the SGT cell, a process for connecting a word-line is added, and the process of forming the silicon pillar and capacitor are complex. Also, the isolation characteristics between the memory cells are poor, and there is a high possibility that a short between a capacitor plate-node and a gate electrode will occur during a process for forming the gate electrode.
Also, U.S. Pat. No. 4,833,516 discloses a memory cell having a transistor and a capacitor of vertical structure. However, such a memory cell has reduced efficiency in terms of cell area utilization.
Further, Toshiyuki Nishihara et al. suggest a silicon-on-insulator (SOI) structure cell wherein a capacitor is completely buried under a silicon layer, so that a memory cell area can be maximized (see IEDM '92, "A Buried Capacitor DRAM Cell with Bonded SOI for 256 M and 1 Gbit DRAMs"). However, in the SOI structure cell, it is difficult to control the remaining thickness during the process for polishing a silicon substrate, and a bit-line contact hole area for connecting the drain region of a transistor with a bit-line is needed.